said the SYN461x is the first in a new family of wireless SoCs designed "from the ground up" for embedding intelligence into ultra-low-power edge devices. Block diagram of the SYN461x SoC.

Terminus Circuits offers best-in-class PHY IP for PCI Express Gen 5/4/3/2/1. The PHY is designed for low latency, low power, small form factor, high interface speeds intended for high performance ...

This special-purpose hard IP block delivers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications including system-on-chip (SoC) to chiplets ...

It has been two years since Samsung and AMD went public with their strategic partnership to deliver "Ultra Low Power ... Exynos and other details." An SoC block diagram was shared too, as below.