The project uses a Nikon sensor and a Xilinx Zynq CPU/FPGA. The idea is the set up and control the CMOS sensor with the CPU side of the Zynq chip, then receive and process the data from the sensor ...

The LDS SATA 3 HOST AHCI XZ7 IP incorporates the AHCI registers model, the Transport layer, the Link layer and the PHY layer on a Xilinx Zynq speed grade 2 FPGA. The LDS_SATA 3 HOST AHCI XZ7 IP is ...

The Zedboard uses Xilinx’s Zynq, which is a combination ARM CPU and FPGA. [Jeff Johnson] recently posted an excellent two-part tutorial covering using a Zedboard with multiple Ethernet ports.

Zagreb, Croatia -- January 7, 2013-- New logiSPI SPI to AXI4 Controller Bridge IP core from Xylon's logicBRICKS™ IP library enables easy inter-chip board-level interfacing between virtually any ...